1. Field of the Invention
The present invention relates to a feedback amplifier circuit, and in particular, to a feedback amplifier circuit which is formed by, for example, a CMOS circuit, is constituted by utilizing a switched operational amplifier and a chopper modulator, and is operable at a low voltage.
2. Description of the Related Art
Recently, a sensor chip employing a mixed signal CMOS technique has been applied to detection and monitoring of a biological function (See, e.g., Non-Patent Documents 1 and 2). A low noise amplifier is one of the most important circuits in the sensor chip, since the sensor chip detects a low-level signal. However, in the scaled CMOS technique, increase in a direct-current (DC) offset voltage and increase in a low frequency (1/f) noise lead to a serious problem.
The auto-zero operation and chopper stabilization are techniques widely used to reduce these noises (See, e.g., Non-Patent Document 3). The principles of these techniques are shown in FIGS. 13 to 18. FIG. 13 is a circuit diagram showing a configuration of an operational amplifier circuit including an auto-zero operational circuit which is one of principles of noise reduction techniques according to a prior art. FIG. 14 is a timing chart showing control signals φ1 and φ2 for use in the operational amplifier circuit of FIG. 13 for offset cancellation.
Referring to FIG. 13, the operational amplifier circuit including the auto-zero operational circuit is constituted by including a differential operational amplifier 50, an operational amplifier 51, a sample-hold circuit 52 and an adder 53 for forming the auto-zero operational circuit, an adder 54 for equivalently considering a DC offset Voff and a 1/f noise Vfn at zero input, and four switches 55 to 58 operating in response to the control signals φ1 and φ2 for the offset cancellation.
Referring to FIG. 14, the control signal φ2 has a high level only during an offset cancellation interval, and the control signal φ1 becomes the high level from a low level after the end of the offset cancellation interval. According to the auto-zero operation technique, noises such as the DC offset Voff and the 1/f noise Vfn at zero input are sampled, and thereafter, a noise effect caused by a feedback is subtracted from an input signal by the auto-zero operational circuit constituted by the operational amplifier 51, the sample-hold circuit 52, and the adder 53. The auto-zero operation technique thus makes it possible to reduce the low-frequency noises of the amplifier circuit, however, one problem of the auto-zero operation technique is to increase in a baseband noise floor caused by aliasing of a broadband noise unique to a sampling process.
FIG. 15 is a circuit diagram showing a configuration of a chopper amplifier circuit of an operational amplifier including a chopper stabilizing circuit, which is one of the principles of noise reduction techniques according to the prior art. FIG. 16 is a timing chart showing control signals φ1 and φ2 for use in the operational amplifier circuit of FIG. 15 for chopper modulation and chopper demodulation. Referring to FIG. 16, the control signals φ1 and φ2 have a predetermined chopper frequency fc and are complementary to each other. In this case, a chopper cycle Tc is a reciprocal of the chopper frequency fc. In addition, FIG. 17 is a diagram showing a frequency characteristic of an input voltage signal Vin(f) inputted to the chopper amplifier circuit of FIG. 15, FIG. 18 is a diagram showing a frequency characteristic of an input voltage signal V(f) inputted to an operational amplifier 60 of the chopper amplifier circuit of FIG. 15, and FIG. 19 is a diagram showing a frequency characteristic of an output voltage signal Vout(f) outputted from a chopper demodulator 62 of the chopper amplifier circuit of FIG. 15, and a frequency characteristic of an output voltage signal outputted from a low-pass filter 63.
Referring to FIG. 15, the chopper amplifier circuit is constituted by including a differential operational amplifier 60, a chopper modulator 61 which is provided at the previous stage of the operational amplifier 60 and constituted by four switches 71 to 74, an adder 64 which is provided at the previous stage of the operational amplifier 60 for equivalently considering the DC offset Voff and the 1/f noise Vfn, the chopper demodulator 62 which is provided at the subsequent stage of the operational amplifier 60 and constituted by four switches 81 to 84, and the low-pass filter 63 which is provided at the subsequent stage of the chopper demodulator 62 and inserted at a final stage of the chopper amplifier circuit for extracting a desired input signal. According to the chopper stabilization based on a modulation technique, a chopper-modulated signal is obtained by converting a frequency range of an input signal having a frequency spectrum of FIG. 17 into a higher frequency range by the chopper modulator 61 (See FIG. 18). The DC offset Voff and the 1/f noise Vfn are added to the chopper-modulated signal at the previous stage of the operational amplifier 60. A resultant chopper-modulated signal is amplified by the operational amplifier 60, is chopper-demodulated by the chopper demodulator 62, and is processed by the low-pass filter 63 so as to obtain an input signal that is an original baseband signal (See FIG. 19). It is noted that a level of the 1/f noise Vfn is smaller than that of a thermal noise. In the chopper amplifier circuit, a large energy due to the low-frequency noise is generated by the chopper modulation using the chopping frequency fc, however, a cleaner output signal can be obtained by using the low-pass filter 63 employed in the chopper stabilization technique.
A combination of the auto-zero operation technique and the chopper stabilization technique can contribute to reduce the baseband noise floor and modulation noise at the chopper frequency, since the auto-zero operation eliminates the DC offset and the chopper stabilization reduces the baseband noise (See, e.g., Non-Patent Document 4).
The above-mentioned two techniques are required for a low noise amplifier operating at a low voltage, however, it is difficult to apply the two techniques to the low noise amplifier by utilizing an ordinary analog switch. The reason for the difficulty is that the analog switch cannot transmit an intermediate voltage level by using a low power source voltage. In order to solve this problem of the analog switch, a clock signal boosting technique (See, e.g., Non-Patent Document 5) and a switched operational amplifier technique (See, e.g., Non-Patent Document 6) have been developed. The above-mentioned reason will be described below in detail with reference to FIGS. 20 and 21.
FIG. 20 is a circuit diagram showing a configuration of a CMOS analog switch circuit according to a prior art. FIG. 21 is a graph showing operation of the CMOS analog switch circuit of FIG. 20 and conductances Gp and Gn of respective MOSFETs P101 and N101 with respect to an input voltage Vin. The conductance Gp of the P channel MOSFET P101 and the conductance Gn of the N channel MOSFET N101, which constitute the CMOS analog switch of FIG. 20, decrease at the input voltage near Vdd/2 even in an ON-state when a power source voltage Vdd is reduced to, for example, one volt, and this leads to that the analog switch cannot be turned on. Under these conditions, there was such a problem that it was difficult to realize an electronic circuit utilizing the analog switch such as an A/D converter, a D/A converter or a DC amplifier circuit.
Namely, in recent fine CMOS processing, the power source voltage Vdd is gradually made lower according to a device scaling law, however, a threshold voltage Vth of a CMOS device is not made lower in order to reduce the power consumption during standby of a large-scaled digital circuit. For example, in a CMOS process with the power source voltage Vdd of 1.0 V and the threshold voltage Vth of 0.5 V, a floating analog switch is put into an off-state when the input signal has an intermediate electric potential, and then, a chopper circuit for switching over among signal paths cannot be realized (See FIGS. 20 and 21). In order to realize the analog switch operating even at a low power source voltage, there have been a boot-strapping technique for boosting a gate voltage of a transistor and a low threshold voltage device for use in analog circuits. However, in the former case, such a device is required that has a withstand voltage higher than that of an ordinary device, and this causes problems such as complication of process, deterioration in reliability, and an increase in circuit area. In addition, in the latter case, there are problems of an increase in a leakage current and deterioration in reliability.
With a view to solving the above-described problems, Non-Patent Document 8 discloses a chopper amplifier circuit which is more simple in circuit construction than the prior arts, has also higher reliability and is operable at a low voltage.
FIG. 22 is a circuit diagram showing a configuration of a chopper amplifier circuit according to a prior art. FIG. 23 is a timing chart showing control signals φ0, φ1 and φ2 for use in the chopper amplifier circuit of FIG. 22. The chopper amplifier circuit according to this prior art is a low noise amplifier operating at a low power source voltage based on auto-zero operation and chopper stabilization. In a low voltage operation for chopper stabilization, an input voltage level is unstable, and therefore, the chopper modulator 61 and the chopper demodulator 62 according to the prior art cannot be implemented in floating analog switches. In order to solve this problem, the chopper amplifier circuit is characterized by including a switched operational amplifier 3 having a negative feedback as shown in FIG. 22.
Referring to FIG. 22, the chopper amplifier circuit according to the prior art includes a chopper modulator 1, an adder 2, a switched operational amplifier 3 including a chopper demodulator 4 provided at a final stage thereof, a chopper modulator 5 for a negative feedback circuit a low-pass filter 6, an input terminal T1, an intermediate output terminal T2, an output terminal T3, a coupling capacitor C1, a capacitor C2 for the negative feedback circuit, and a switch 7 and a terminal T4 for the auto-zero operation. Referring to FIG. 23, during an offset sampling (which is preferably a time interval of 1 to 5 μsec and executed at a frequency of 1 Hz or lower), or during an auto-zero operation interval, the control signal φ0 indicating an interval during which the switch 7 is turned on and the control signal φ1 for the chopper modulation and the chopper demodulation become both a high level, while the control signal φ2 which is a complementary signal to the control signal φ1 becomes a low level. Next, in a chopper amplification interval, the control signal φ0 holds the low level, the control signal φ1 becomes a repeating rectangular pulse signal, and the control signal φ2 becomes a repeating rectangular pulse signal which is a complementary signal to the control signal φ1.
Referring to FIG. 22, an input signal Vin, which is either a DC signal or a low frequency signal inputted to the input terminal T1, is inputted to the chopper modulator 1, which is a multiplier, via the coupling capacitor C1. The chopper modulator 1 multiplies the input signal Vin by the control signal φ1 (or φ2), and outputs a chopper-modulated signal indicating a multiplication result to the adder 2. During the offset sampling for the auto-zero operation interval, the adder 2 subtracts an auto-zero operation offset signal, which is fed back via the switch 7 and the terminal T4, from the chopper-modulated signal. In addition, during the chopper amplification interval, the adder 2 subtracts a chopper-modulated signal, which is outputted from the chopper modulator 5 of the negative feedback circuit, from the chopper-modulated signal, and thereafter, the adder 2 outputs a signal indicating a subtraction result to the switched operational amplifier 3.
The switched operational amplifier 3 is constituted by including an input stage, a phase compensation amplifying stage, an auto-zero operation output stage, and the chopper demodulator 4 which is a final stage and which performs chopper demodulation. The switched operational amplifier 3 amplifies an inputted signal while phase-compensating the inputted signal, then chopper-demodulates an amplified signal according to the control signal φ1 (or φ2), and outputs an output signal Vout after the chopper demodulation to the low-pass filter 6 via the intermediate output terminal T2. In addition, the switched operational amplifier 3 outputs the output signal Vout to the chopper modulator 5 via the capacitor C2 for the feedback circuit. In this case, the capacitor C2 accumulates and holds a DC offset voltage at an output terminal of the chopper demodulator 4 during the auto-zero operation interval so as to cancel an offset voltage at an input terminal of the switched operational amplifier 3 during the chopper amplification interval after the auto-zero operation interval by the DC offset voltage accumulated and held in the capacitor C2. In addition, an output signal outputted from the auto-zero operation output stage of the switched operational amplifier 3 is fed back to the adder 2 as an auto-zero operation signal Vaz, via the switch 7, which is turned on only during the offset sampling for the auto-zero operation interval, and the terminal T4. The chopper modulator 5 chopper-modulates a feed back signal from the capacitor C2 according to the control signal φ1 (or φ2), and thereafter, outputs a resultant signal to the adder 2. Further, the low-pass filter 6 low-pass-filters the output signal Vout inputted thereto via the intermediate output terminal T2 so as to pass therethrough only a desired frequency component of the input signal, and outputs the low-pass-filtered output signal to the terminal T3 as an amplified input signal.
The documents related to the present invention are as follows:
Non-Patent Document 1: K. D. Wise, “Wireless implantable Microsystems: Coming breakthroughs in health care”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 106-109, June 2002;
Non-Patent Document 2: T. Yoshida et al., “A design of neural signal sensing LSI with multi-input-channels”, IEICE Transactions Fundamentals, Vol. E87-A, No. 2, pp. 376-383, February 2004;
Non-Patent Document 3: C. C. ENZ et al., “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, Proceedings of the IEEE, Vol. 84, No. 11, pp. 1584-1614, November 1996;
Non-Patent Document 4: A. T. K. Tang, “A 3 mV-Offset Operational Amplifier with 20 μV/√{square root over ((Hz))} Input Noise PSD at DC Employing both Chopping and Autozeroing”, ISSCC Digest of Technical Papers, pp. 386-387, February 2002;
Non-Patent Document 5: A. M. Abo et al., “A 1.5-V, 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter”, Journal of Solid State Circuits, Vol. 34, No. 5, pp. 599-606, May 1999;
Non-Patent Document 6: V. Cheung et al., “A 1V CMOS Switched-Opamp Switched-Capacitor Pseudo-2-Path Filter”, ISSCC Digest of Technical Papers, pp. 154-155, February 2000;
Non-Patent Document 7: Q. Huang, C. Menolfi, “A 200 nV offset 6.5 nV/√{square root over ((Hz))} Noise PSD 5.6 kHz Chopper Instrumentation Amplifier in 1 μm Digital CMOS”, ISSCC Digest of Technical Papers, pp. 362-363, February 2001;
Non-Patent Document 8: J. F. Duque-Carrillo et al., “1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology”, Journal of Solid State Circuits, Vol. 35, No. 1, pp. 33-44, January 2000; and
Non-Patent Document 9: T. Yoshida, “A 1V Supply 50 nV/√{square root over ((Hz))} Noise PSD CMOS Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization”, Symposium on VLSI, pp. 118-121, 2005.
However, in the chopper amplifier circuit according to the prior art disclosed in Non-Patent Document 8, since the DC offset voltage of the operational amplifier is held in the capacitors C1, C2, it would be necessary to increase the capacitance value in order to reduce decrease in the hold voltage due to leakage, which would lead to a problem of an increase in the layout area. Also, since the DC offset voltage is present between a pair of virtual grounding points of the fully-differential operational amplifier, there has been a problem of occurrence of an on-resistance of the chopper modulation circuit and clock feed-through mismatch (i.e., when the gate switch is turned on or off, the voltage applied to the gate causes noise to occur on the output side).